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20 cycles or 52 cycles interrupt disable?

Posted: Wed Sep 12, 2007 2:16 pm
by gda
Hi,

In usbdrv.h I read:

Interrupt latency:
The application must ensure that the USB interrupt is not disabled for more
than 20 cycles.


In usbdrvasm165.S I read:

max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable


Can somebody explain me the difference? Sorry if this is a stupid question, I am completely new to
micro controller programming.

Inspired by the project from Dick Streefland I would like to find out whether it would be possible
to use parts of his code for an infrared receiver together with the AVR-USB code on a attiny45
with the internal rc oscillator. The first problem I see is that his interrupt routines need more
than 20 cycles, but they have less than 52 cycles.
The other problem I have found is, that he uses a 16bit timer, but the attiny45 has none. I have
to learn more to understand whether he really need this fine resolution, but I doubt it, because he only
saves the marks and spaces of the IR signal as bytes.

Gerald

Posted: Wed Sep 12, 2007 6:28 pm
by christian
The statement in usbdrv.h is for the worst case of the 12 MHz module. Timing is more relaxed if you switch to 16.5 MHz. Therefore the discrepancy.

Posted: Wed Sep 12, 2007 9:25 pm
by Guest
christian wrote:The statement in usbdrv.h is for the worst case of the 12 MHz module. Timing is more relaxed if you switch to 16.5 MHz. Therefore the discrepancy.


Thank you for the fast reply, I didn't expect a so big difference. %30 faster
and more than %100 more cycles is astonishing. This are good news.

Gerald

Posted: Wed Sep 12, 2007 10:14 pm
by christian
I think (would have to check the source to be sure), the 20 cycles were for an older version. The current release may allow longer latencies even at 12 MHz.

Re:

Posted: Wed Jul 15, 2009 1:38 pm
by Yang
can you explain how the interrupt latency is calculated in more detail? thanks!

Re: 20 cycles or 52 cycles interrupt disable?

Posted: Wed Jul 15, 2009 3:19 pm
by christian
You must look at the assembler listing and count the CPU cycles between every CLI and SEI instruction pair and the length of all interrupt routines until they either hit RETI or SEI. The longest count plus ~ 10 cycles is your maximum interrupt latency.