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	<title>Objective Development Forums</title>
	
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	<updated>2009-07-15T15:19:43+02:00</updated>

	<author><name><![CDATA[Objective Development Forums]]></name></author>
	<id>https://forums.obdev.at/app.php/feed/topic/740</id>

		<entry>
		<author><name><![CDATA[christian]]></name></author>
		<updated>2009-07-15T15:19:43+02:00</updated>

		<published>2009-07-15T15:19:43+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=10167#p10167</id>
		<link href="https://forums.obdev.at/viewtopic.php?t=740&amp;p=10167#p10167"/>
		<title type="html"><![CDATA[Re: 20 cycles or 52 cycles interrupt disable?]]></title>

		
		<content type="html" xml:base="https://forums.obdev.at/viewtopic.php?t=740&amp;p=10167#p10167"><![CDATA[
You must look at the assembler listing and count the CPU cycles between every CLI and SEI instruction pair and the length of all interrupt routines until they either hit RETI or SEI. The longest count plus ~ 10 cycles is your maximum interrupt latency.<p>Statistics: Posted by <a href="https://forums.obdev.at/memberlist.php?mode=viewprofile&amp;u=8">christian</a> — Wed Jul 15, 2009 3:19 pm</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[Anonymous]]></name></author>
		<updated>2009-07-15T13:38:21+02:00</updated>

		<published>2009-07-15T13:38:21+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=10165#p10165</id>
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		<title type="html"><![CDATA[Re:]]></title>

		
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can you explain how the interrupt latency is calculated in more detail? thanks!<p>Statistics: Posted by Guest — Wed Jul 15, 2009 1:38 pm</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[christian]]></name></author>
		<updated>2007-09-12T22:14:14+02:00</updated>

		<published>2007-09-12T22:14:14+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=2348#p2348</id>
		<link href="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2348#p2348"/>
		<title type="html"><![CDATA[20 cycles or 52 cycles interrupt disable?]]></title>

		
		<content type="html" xml:base="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2348#p2348"><![CDATA[
I think (would have to check the source to be sure), the 20 cycles were for an older version. The current release may allow longer latencies even at 12 MHz.<p>Statistics: Posted by <a href="https://forums.obdev.at/memberlist.php?mode=viewprofile&amp;u=8">christian</a> — Wed Sep 12, 2007 10:14 pm</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[Anonymous]]></name></author>
		<updated>2007-09-12T21:25:04+02:00</updated>

		<published>2007-09-12T21:25:04+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=2346#p2346</id>
		<link href="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2346#p2346"/>
		<title type="html"><![CDATA[20 cycles or 52 cycles interrupt disable?]]></title>

		
		<content type="html" xml:base="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2346#p2346"><![CDATA[
<blockquote><div><cite>christian wrote:</cite>The statement in usbdrv.h is for the worst case of the 12 MHz module. Timing is more relaxed if you switch to 16.5 MHz. Therefore the discrepancy.</div></blockquote><br /><br />Thank you for the fast reply, I didn't expect a so big difference. %30 faster<br />and more than %100 more cycles is astonishing. This are good news.<br /><br />Gerald<p>Statistics: Posted by Guest — Wed Sep 12, 2007 9:25 pm</p><hr />
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	</entry>
		<entry>
		<author><name><![CDATA[christian]]></name></author>
		<updated>2007-09-12T18:28:12+02:00</updated>

		<published>2007-09-12T18:28:12+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=2339#p2339</id>
		<link href="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2339#p2339"/>
		<title type="html"><![CDATA[20 cycles or 52 cycles interrupt disable?]]></title>

		
		<content type="html" xml:base="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2339#p2339"><![CDATA[
The statement in usbdrv.h is for the worst case of the 12 MHz module. Timing is more relaxed if you switch to 16.5 MHz. Therefore the discrepancy.<p>Statistics: Posted by <a href="https://forums.obdev.at/memberlist.php?mode=viewprofile&amp;u=8">christian</a> — Wed Sep 12, 2007 6:28 pm</p><hr />
]]></content>
	</entry>
		<entry>
		<author><name><![CDATA[Anonymous]]></name></author>
		<updated>2007-09-12T14:16:54+02:00</updated>

		<published>2007-09-12T14:16:54+02:00</published>
		<id>https://forums.obdev.at/viewtopic.php?t=740&amp;p=2335#p2335</id>
		<link href="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2335#p2335"/>
		<title type="html"><![CDATA[20 cycles or 52 cycles interrupt disable?]]></title>

		
		<content type="html" xml:base="https://forums.obdev.at/viewtopic.php?t=740&amp;p=2335#p2335"><![CDATA[
Hi, <br /><br />In usbdrv.h I read:<br /><br /><blockquote class="uncited"><div>Interrupt latency:<br />The application must ensure that the USB interrupt is not disabled for more<br />than 20 cycles.</div></blockquote><br /><br />In usbdrvasm165.S I read:<br /><br /><blockquote class="uncited"><div>max allowable interrupt latency: 59 cycles -&gt; max 52 cycles interrupt disable</div></blockquote><br /><br />Can somebody explain me the difference? Sorry if this is a stupid question, I am completely new to<br />micro controller programming.<br /><br />Inspired by the project from Dick Streefland I would like to find out whether it would be possible<br />to use parts of his code for an infrared receiver together with the AVR-USB code on a attiny45<br />with the internal rc oscillator. The first problem I see is that his interrupt routines need more<br />than 20 cycles, but they have less than 52 cycles. <br />The other problem I have found is, that he uses a 16bit timer, but the attiny45 has none. I have<br />to learn more to understand whether he really need this fine resolution, but I doubt it, because he only<br />saves the marks and spaces of the IR signal as bytes.<br /><br />Gerald<p>Statistics: Posted by Guest — Wed Sep 12, 2007 2:16 pm</p><hr />
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