Objective Development Forums 2011-11-18T20:59:51+02:00 https://forums.obdev.at/app.php/feed/topic/6205 2011-11-17T12:59:11+02:00 2011-11-17T12:59:11+02:00 https://forums.obdev.at/viewtopic.php?t=6205&p=20214#p20214 <![CDATA[Re: HIDKeys + ATMEGA16]]> In the main loop, only call usbPoll(); for now, until it works.
Use a known working descriptor. I always use the hid-mouse example to test new v-usb hardware.
Make sure your pin configuration matches (usbconfig.h), because the hardware you linked doesn't match the reference design of using PD2 and PD3.

FYI: Your computer will try to enumerate the device even without any firmware in the controller. This is due to the pullup on D-

Statistics: Posted by Daid — Thu Nov 17, 2011 12:59 pm

]]> 2011-11-18T20:59:51+02:00 2011-11-16T22:25:46+02:00 https://forums.obdev.at/viewtopic.php?t=6205&p=20207#p20207 <![CDATA[solved: HIDKeys + ATMEGA16]]>
I'm in desperate need for some assistance as I spent hours trying to get the HIDKeys to work on some MJoy16 hardware I had lying around. This is a firmware only joystick device, which is closed source and built according to this schematic: http://www.joysticks.ru/download/files/MJoy16_v1.pdf. The hardware works, when flashed with the closed source firmware I have a working joystick device.

Now for the changes I made to the HIDKeys example:

usbconfig.h:
no changes

main.c:

Code: 

static void hardwareInit(void)
{
uchar   i, j;

    PORTB = 0xff;   /* activate all pull-ups */
    DDRB = 0;       /* all pins input */
    PORTC = 0xff;   /* activate all pull-ups */
    DDRC = 0;       /* all pins input */
    PORTD = 0xfa;   /* 1111 1010 bin: activate pull-ups except on USB lines */
    DDRD = 0x07;    /* 0000 0111 bin: all pins input except USB (-> USB reset) */
   j = 0;
   while(--j){     /* USB Reset by device only required on Watchdog Reset */
      i = 0;
      while(--i); /* delay >10ms for USB reset */
   }
    DDRD = 0;    /* 0000 0000 bin: remove USB reset condition */
    /* configure timer 0 for a rate of 12M/(1024 * 256) = 45.78 Hz (~22ms) */
    TCCR0 = 5;      /* timer 0 prescaler: 1024 */
}

changed the second DDRD call from 0x02 to 0, because the D+ line is also connected to PD1 in my hardware. I don't want that pin to drive that line, so I set it to input (0).

Code: 

int   main(void){

uchar   key, lastKey = 0, keyDidChange = 0;
uchar   idleCounter = 0;

   //wdt_enable(WDTO_2S);
   wdt_disable();
       hardwareInit();
   //odDebugInit();
   usbInit();
   sei();
       //DBG1(0x00, 0, 0);
   for(;;){   /* main event loop */
      //wdt_reset();
      usbPoll();
      
         [...]


disabled all the watchdog timer calls, as I'm not a friend of watchdogs during development, even included a wdt_disable()-call. Also disabled the debugs.

Makefile:

Code: 

COMPILE = avr-gcc -Wall -Iusbdrv -I. -mmcu=atmega16 #-DDEBUG_LEVEL=1

set AVR type to ATMEGA16 and disabled size optimisation, thought this might help. But same result with optimisation.

Other than that everything is "as shipped"

my fusebits are:
high: 0b10001001
low: 0b10011111

and my problem: well, "unable to enumerate USB device at port 1"
I'm new to USB so the usbmon logs don't really tell me anything, maybe they are of help to you:

Code: 

ffff8800414756c0 2808119433 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff8800414756c0 2808119451 C Ci:2:001:0 0 4 = 01030100
ffff8800414756c0 2808119456 S Co:2:001:0 s 23 01 0010 0001 0000 0
ffff8800414756c0 2808119464 C Co:2:001:0 0 0
ffff8800414756c0 2808119468 S Ci:2:001:0 s a3 00 0000 0002 0004 4 <
ffff8800414756c0 2808119474 C Ci:2:001:0 0 4 = 00010000
ffff88005c08a240 2808226937 S Ii:2:001:1 -115:128 2 <
ffff8800414756c0 2808226971 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff8800414756c0 2808226980 C Ci:2:001:0 0 4 = 01030000
ffff8800414756c0 2808226993 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff8800414756c0 2808227000 C Co:2:001:0 0 0
ffff880041475840 2808289432 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880041475840 2808289463 C Ci:2:001:0 0 4 = 03030000
ffff880041475840 2808349430 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880041475840 2808349437 C Co:2:001:0 0 0
ffff880041475840 2808349455 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880041475840 2808353467 C Ci:2:000:0 -71 0
ffff880041475840 2808353488 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880041475840 2808357464 C Ci:2:000:0 -71 0
ffff880041475840 2808357483 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880041475840 2808361466 C Ci:2:000:0 -71 0
ffff880045070d80 2808361490 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2808361498 C Co:2:001:0 0 0
ffff88005c08a240 2808379431 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2808379434 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2808416927 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2808416954 C Ci:2:001:0 0 4 = 03030000
ffff880045070d80 2808476934 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2808476939 C Co:2:001:0 0 0
ffff880045070d80 2808589445 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2808593464 C Ci:2:000:0 -71 0
ffff880045070d80 2808593485 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2808597467 C Ci:2:000:0 -71 0
ffff880045070d80 2808597487 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2808601464 C Ci:2:000:0 -71 0
ffff880045070d80 2808601485 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2808601493 C Co:2:001:0 0 0
ffff88005c08a240 2808629448 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2808629453 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2808659438 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2808659469 C Ci:2:001:0 0 4 = 03030000
ffff880045070d80 2808716943 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2808716948 C Co:2:001:0 0 0
ffff880045070d80 2808826945 S Co:2:001:0 s 23 01 0001 0001 0000 0
ffff880045070d80 2808826955 C Co:2:001:0 0 0
ffff880045070d80 2808826973 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2808826980 C Co:2:001:0 0 0
ffff880045070d80 2808889438 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2808889448 C Ci:2:001:0 0 4 = 01030200
ffff880045070d80 2808946944 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2808946954 C Ci:2:001:0 0 4 = 01030200
ffff88005c08a240 2809128142 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2809128148 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2809157406 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2809157419 C Ci:2:001:0 0 4 = 01030200
ffff880045070d80 2809366946 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2809366958 C Ci:2:001:0 0 4 = 01030200
ffff880045070d80 2809366963 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2809366971 C Co:2:001:0 0 0
ffff88005c08a240 2809379447 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2809379453 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2809576943 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2809576973 C Ci:2:001:0 0 4 = 03030000
ffff88005c08a240 2809629446 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2809629451 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2809639432 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2809639438 C Co:2:001:0 0 0
ffff880045070d80 2809639457 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809643464 C Ci:2:000:0 -71 0
ffff880045070d80 2809643485 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809647462 C Ci:2:000:0 -71 0
ffff880045070d80 2809647479 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809651463 C Ci:2:000:0 -71 0
ffff880045070d80 2809651487 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2809651494 C Co:2:001:0 0 0
ffff880045070d80 2809706945 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2809706975 C Ci:2:001:0 0 4 = 03030000
ffff880045070d80 2809769440 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2809769446 C Co:2:001:0 0 0
ffff88005c08a240 2809879446 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2809879452 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2809879612 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809883464 C Ci:2:000:0 -71 0
ffff880045070d80 2809883519 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809887465 C Ci:2:000:0 -71 0
ffff880045070d80 2809887518 S Ci:2:000:0 s 80 06 0100 0000 0040 64 <
ffff880045070d80 2809891463 C Ci:2:000:0 -71 0
ffff880045070d80 2809891568 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2809891578 C Co:2:001:0 0 0
ffff880045070d80 2809946943 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2809946974 C Ci:2:001:0 0 4 = 03030000
ffff880045070d80 2810009440 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2810009446 C Co:2:001:0 0 0
ffff880045070d80 2810116943 S Co:2:001:0 s 23 01 0001 0001 0000 0
ffff880045070d80 2810116953 C Co:2:001:0 0 0
ffff880045070d80 2810116971 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2810116979 C Co:2:001:0 0 0
ffff88005c08a240 2810129446 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2810129452 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2810176947 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070d80 2810176977 C Ci:2:001:0 0 4 = 03030000
ffff880045070d80 2810236943 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070d80 2810236948 C Co:2:001:0 0 0
ffff880045070d80 2810236965 S Co:2:000:0 s 00 05 000e 0000 0000 0
ffff880045070d80 2810240461 C Co:2:000:0 -71 0
ffff88005c08a240 2810379446 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2810379451 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2810449439 S Co:2:000:0 s 00 05 000e 0000 0000 0
ffff880045070d80 2810453461 C Co:2:000:0 -71 0
ffff88005c08a240 2810629445 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2810629451 S Ii:2:001:1 -115:128 2 <
ffff880045070d80 2810656948 S Co:2:001:0 s 23 01 0001 0001 0000 0
ffff880045070d80 2810656959 C Co:2:001:0 0 0
ffff880045070d80 2810656976 S Co:2:001:0 s 23 03 0004 0001 0000 0
ffff880045070d80 2810656983 C Co:2:001:0 0 0
ffff880045070540 2810716943 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070540 2810716972 C Ci:2:001:0 0 4 = 03030000
ffff880045070540 2810776944 S Co:2:001:0 s 23 01 0014 0001 0000 0
ffff880045070540 2810776949 C Co:2:001:0 0 0
ffff880045070540 2810776964 S Co:2:000:0 s 00 05 000f 0000 0000 0
ffff880045070540 2810780460 C Co:2:000:0 -71 0
ffff88005c08a240 2810876989 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2810876996 S Ii:2:001:1 -115:128 2 <
ffff880045070540 2810986945 S Co:2:000:0 s 00 05 000f 0000 0000 0
ffff880045070540 2810990460 C Co:2:000:0 -71 0
ffff88005c08a240 2811126949 C Ii:2:001:1 0:128 1 = 02
ffff88005c08a240 2811126954 S Ii:2:001:1 -115:128 2 <
ffff880045070540 2811196952 S Co:2:001:0 s 23 01 0001 0001 0000 0
ffff880045070540 2811196963 C Co:2:001:0 0 0
ffff880045070540 2811196981 S Co:2:001:0 s 23 01 0001 0001 0000 0
ffff880045070540 2811196987 C Co:2:001:0 0 0
ffff880045070540 2811196994 S Ci:2:001:0 s a3 00 0000 0001 0004 4 <
ffff880045070540 2811197002 C Ci:2:001:0 0 4 = 01030200
ffff880045070540 2811197005 S Co:2:001:0 s 23 01 0011 0001 0000 0
ffff880045070540 2811197011 C Co:2:001:0 0 0
ffff88005c08a240 2813856952 C Ii:2:001:1 -2:128 0

( a bit lengthy)
I also used wireshark, hoping that it might be a bit clearer to me what is (not) happening. Ah, well, it says "malformed packet" in the GET_DESCRIPTOR response. Now what?

So, could anyone pleeeeaaase help me? What am I doing wrong? I spent days fiddling around with this, thinking "it can't be that hard", well, mistaken.
I hope you have all the info you need.
THX folks


edit: SOLVED
problem was the pin setup. As PD1 is also connected to PD2 I had to set PD1 to input and disable the pull-up as it is done with the USB line. This war PD1 does not accidentally drive a USB line.

Statistics: Posted by TheDude — Wed Nov 16, 2011 10:25 pm

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